RFR: 8351949: RISC-V: Cleanup and enable store-load peephole for membars [v8]

[Robbin Ehn]

On Thu, 3 Apr 2025 06:18:24 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3558:
>> 
>>> 3556: 
>>> 3557: void MacroAssembler::membar(uint32_t order_constraint) {
>>> 3558:   if (UseZtso && ((order_constraint & StoreLoad) != StoreLoad)) {
>> 
>> An assert in Assembler::fence() could help to catch potential misuse in the future:
>> `assert(!UseZtso || ((order_constraint & StoreLoad) == StoreLoad)`
>
> Sorry, I now understand, you mean after doing all these checks if we can elide.
> 
> Yes, that seems good.

It's not possible as rv pause is encoded as "fence w, 0".

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PR Review Comment: https://git.openjdk.org/jdk/pull/24035#discussion_r2026295481