RFR: 8353572: x86: AMD platforms miss the check for CLWB feature flag

[Vladimir Ivanov]

On Tue, 8 Apr 2025 18:41:21 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

>> src/hotspot/cpu/x86/vm_version_x86.cpp line 3100:
>> 
>>> 3098:     if (ext_cpuid1_ecx.bits.sse4a != 0)
>>> 3099:       result |= CPU_SSE4A;
>>> 3100:     if (sef_cpuid7_ebx.bits.clwb != 0)
>> 
>> I'm curious what's the rule here when it comes to vendor-specific features? 
>> 
>> From what I'm seeing in the sources, both AMD and ZX enumerate only `ext_cpuid1` features while for Intel it's a mix of `sef_cpuid7` and `ext_cpuid1`.
>> 
>> So, I'm curious whether the code should be moved up and shared for all CPUs.
>
> Are you happy with this explanation, @iwanowww?

Well, not really. If it were like that, then all CPU sensing logic on x86 would have been vendor-specific. But it's not the case: among many features x86 CPUs may declare, just a few are treated as vendor-specific. 

I took a look at how it was handled before and many extensions Intel introduced were not guarded by `is_intel()` check in the first place.

And there's even more to that: though `CPU_LZCNT` and `CPU_3DNOW_PREFETCH` are handled as vendor-specific, both of them are treated uniformly across all 3 cpu families. Can those be moved into vendor-agnostic part now? 

Overall, I'm more comfortable with moving the check rather than duplicating it in AMD-specific block.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24385#discussion_r2034114405