RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads [v2]

[Andrew Haley]

On Tue, 19 Aug 2025 13:42:19 GMT, Samuel Chee <duke at openjdk.org> wrote:

>> Replaces the DMB ISH + LD + DMB ISHLD sequence with LDAR for volatile field loads - for example, AtomicLong::get.
>> 
>> This is valid, as originally the DMBs were necessary due to the case described here - https://bugs.openjdk.org/browse/JDK-8179954. As in the rare case where the LD can be reordered with an LDAR or STLR from the C2 implementation for stores and loads, these DMBs are required.
>> However, acquire/release operations use a sequentially consistent model which does not allow reordering between them. Hence, the LD can be replaced with an LDAR to disallow reordering with a STLR/LDAR and the first DMB can be removed.
>> 
>> The LDAR has acquire semantics, so it's impossible for memory accesses after to be reordered before; the DMB ISHLD is not required. Therefore, a singular LDAR is sufficient.
>
> Samuel Chee has updated the pull request incrementally with two additional commits since the last revision:
> 
>  - Address review comments
>    
>    Change-Id: Ica13be8094ac0f057066042ef0a5ec5927b98dfd
>  - Refine code generation for mem2reg_volatile
>    
>    The patch is contributed by @theRealAph.
>    
>    Change-Id: I7ab1854dd238cdce72a4ab218b5b4ee84ad39586

src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp line 1410:

> 1408:   // be atomic - which includes unaligned ones - use the generic DMB + LD sequence, as LDAR might
> 1409:   // fault for unaligned accesses.
> 1410:   if (AlwaysAtomicAccesses) {

I'm not sure this makes sense. Misaligned accesses can't ever be atomic.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26748#discussion_r2285353492