RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads [v2]

[Samuel Chee]

On Tue, 19 Aug 2025 13:54:07 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Samuel Chee has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Address review comments
>>    
>>    Change-Id: Ica13be8094ac0f057066042ef0a5ec5927b98dfd
>>  - Refine code generation for mem2reg_volatile
>>    
>>    The patch is contributed by @theRealAph.
>>    
>>    Change-Id: I7ab1854dd238cdce72a4ab218b5b4ee84ad39586
>
> src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp line 1410:
> 
>> 1408:   // be atomic - which includes unaligned ones - use the generic DMB + LD sequence, as LDAR might
>> 1409:   // fault for unaligned accesses.
>> 1410:   if (AlwaysAtomicAccesses) {
> 
> I'm not sure this makes sense. Misaligned accesses can't ever be atomic.

Yes, so the flag experimental flag `AlwaysAtomicAccesses` will attempt to force to make all accesses atomic - even misaligned ones which causes a memory access error if using LDAR. Hence we resort to the old code sequence when this flag is active.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26748#discussion_r2285491168