RFR: 8351101: RISC-V: C2: Small improvement to MacroAssembler::revb

[Feilong Jiang]

On Tue, 4 Mar 2025 01:28:32 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Hi, please review this small improvement.
> After logic shift right 56 bits, there is no need to zero extend the remaining 8-bit value.
> The reason is that the upper bits will be all zeros as this is a logic shift right.
> Testing: `hotspot:tier1` is clean on linux-riscv64 platform with this change.

Looks fine.

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Marked as reviewed by fjiang (Committer).

PR Review: https://git.openjdk.org/jdk/pull/23879#pullrequestreview-2656075025