RFR: 8345298: RISC-V: Add riscv backend for Float16 operations - scalar [v5]

[Fei Yang]

On Mon, 10 Mar 2025 17:21:47 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/riscv.ad line 4975:
>> 
>>> 4973: 
>>> 4974:   ins_pipe(fp_load_constant_s);
>>> 4975: %}
>> 
>> Can we put this two after `loadConD0`? Then we have a more consistent order for the three variants (F->D->FH) at each place.
>
> In fact, in my mind the order should be FH->F->D, considering the width changing from 16->32->64.

That's also fine to me. Just expecting a consistent order for other definitions as well like `immHF0` -> `immF0` -> `immD0`.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23844#discussion_r1988200318