RFR: 8351666: [PPC64] Make non-volatile VectorRegisters available for C2 register allocation [v24]

[Richard Reingruber]

On Wed, 14 May 2025 10:36:54 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>> src/hotspot/cpu/ppc/ppc.ad line 2013:
>> 
>>> 2011:       int dst_offset = ra_->reg2offset(dst_lo);
>>> 2012:       if (PowerArchitecturePPC64 >= 9) {
>>> 2013:         if (is_aligned(dst_offset, 16)) {
>> 
>> If `Matcher::_new_SP` would be aligned to 16 bytes then the offset here would always be also 16 byte aligned. Can be handled separately from this pr.
>
> Changing to `_new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)stack_alignment_in_slots()));` should solve it for PPC64.  But I don't know if such a change would be appreciated for other platforms. Some platforms have larger vectors than `StackAlignmentInBytes` and they seem to work fine with 8 Byte aligned vector stack slots. PPC64 actually also works fine with the current alignment, except that it requires an additional add instruction which is a bit ugly.

That's correct. The alignment is done in the virtual register file without wasting real stack slots (it corresponds to [pad0](https://github.com/openjdk/jdk/blob/5c73dfc28cbd6801ac85c6685fb8c77aad3ab0b7/src/hotspot/cpu/x86/x86_64.ad#L1921)).
Looks like aarch64 needs [extra instructions](https://github.com/openjdk/jdk/blob/5c73dfc28cbd6801ac85c6685fb8c77aad3ab0b7/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp#L3763) too if the SP offset isn't aligned.
There's code that aligns the spill masks for vectors. It makes no sense if the spill area isn't aligned properly. I'm planning to open a bug and pr when I find the time...

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PR Review Comment: https://git.openjdk.org/jdk/pull/23987#discussion_r2088676125