RFR: 8370947: Mitigate Neoverse-N1 erratum 1542419 negative impact on GenZGC performance [v4]

[Evgeny Astigeevich]

On Thu, 20 Nov 2025 16:35:17 GMT, Evgeny Astigeevich <eastigeevich at openjdk.org> wrote:

>> We cannot execute `tlbi vae3is` here because it requires EL3. We are at EL0.
>
> Or you mean `IC IVAU`?`

I replaced the call of `ICache::invalidate_word()` with:

    asm volatile("dsb ish       \n"
                 "ic  ivau, xzr \n"
                 "isb           \n"
                 : : : "memory");


The code executed in `ICache::invalidate_word()` when all checks are done:

dsb ish
ic  ivau
dsb ish
isb


I use `xzr` in `ic  ivau` because an address in it does not matter. The instruction is trapped and ignored.
I think we don't need the second `dsb` because we will have `dsb sy` in the trap handler.

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PR Review Comment: https://git.openjdk.org/jdk/pull/28328#discussion_r2560695024