RFR: 8370947: Mitigate Neoverse-N1 erratum 1542419 negative impact on GenZGC performance [v6]

[Erik Österlund]

On Tue, 25 Nov 2025 16:41:35 GMT, Evgeny Astigeevich <eastigeevich at openjdk.org> wrote:

>> Or you mean `IC IVAU`?`
>
> I replaced the call of `ICache::invalidate_word()` with:
> 
>     asm volatile("dsb ish       \n"
>                  "ic  ivau, xzr \n"
>                  "isb           \n"
>                  : : : "memory");
> 
> 
> The code executed in `ICache::invalidate_word()` when all checks are done:
> 
> dsb ish
> ic  ivau
> dsb ish
> isb
> 
> 
> I use `xzr` in `ic  ivau` because an address in it does not matter. The instruction is trapped and ignored.
> I think we don't need the second `dsb` because we will have `dsb sy` in the trap handler.

I don't know if we want to jeapordize the correctness of the JVM code based on the exact instructions that are *currently* used to mitigate this issue in the kernel. Eliding the trailing dsb ish because we know the kernel mitigation runs it, seems unnecessarily fragile to me; if the kernel comes up with some smarter and cheaper way of mitigating this in the future, using some other magic incantation, then I don't want to have a correctness issue because of that implicit assumption.

Is it noticeably expensive to run the trailing dsb again?

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/28328#discussion_r2564211770