RFR: 8370947: Mitigate Neoverse-N1 erratum 1542419 negative impact on GenZGC performance [v6]

[Evgeny Astigeevich]

On Wed, 26 Nov 2025 09:27:31 GMT, Erik Österlund <eosterlund at openjdk.org> wrote:

>> I replaced the call of `ICache::invalidate_word()` with:
>> 
>>     asm volatile("dsb ish       \n"
>>                  "ic  ivau, xzr \n"
>>                  "isb           \n"
>>                  : : : "memory");
>> 
>> 
>> The code executed in `ICache::invalidate_word()` when all checks are done:
>> 
>> dsb ish
>> ic  ivau
>> dsb ish
>> isb
>> 
>> 
>> I use `xzr` in `ic  ivau` because an address in it does not matter. The instruction is trapped and ignored.
>> I think we don't need the second `dsb` because we will have `dsb sy` in the trap handler.
>
> I don't know if we want to jeapordize the correctness of the JVM code based on the exact instructions that are *currently* used to mitigate this issue in the kernel. Eliding the trailing dsb ish because we know the kernel mitigation runs it, seems unnecessarily fragile to me; if the kernel comes up with some smarter and cheaper way of mitigating this in the future, using some other magic incantation, then I don't want to have a correctness issue because of that implicit assumption.
> 
> Is it noticeably expensive to run the trailing dsb again?

Yes, we need dsb if we use ic, according to the Arm manual. They are redundant if we have hardware instruction cache coherence enable. On one side we know that the hardware icache coherence is working and ic is ignored. On another side, we check the hardware icache coherence is disabled and we should follow Arm ARM.

I don't expect that having dsb has noticeable performance impact. I haven't seen any. 
I agree with prioritizing correctness.

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PR Review Comment: https://git.openjdk.org/jdk/pull/28328#discussion_r2564406749