RFR: 8367066: RISC-V: refine register selection in MacroAssembler:: decode_klass_not_null

[Fei Yang]

On Mon, 8 Sep 2025 08:57:15 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review this patch?
> 
> Previously, the register selection in MacroAssembler:: decode_klass_not_null is misleading, better to refine it to improve the readability.
> 
> Thanks!
> 
> Running runtime test tier1/2/3...

Yes, we still need one extra change to guarantee that dst != tmp, which we can do with a TEMP_DEF effect for dst. 
I tried adding this change and it seems to work. 


@@ -8936,7 +8941,7 @@ instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
   match(Set dst (DecodeNKlass src));

-  effect(TEMP tmp);
+  effect(TEMP_DEF dst, TEMP tmp);

   ins_cost(ALU_COST);
   format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}

-------------

PR Comment: https://git.openjdk.org/jdk/pull/27138#issuecomment-3268370293