RFR: 8367066: RISC-V: refine register selection in MacroAssembler:: decode_klass_not_null

[Hamlin Li]

On Mon, 8 Sep 2025 23:47:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Yes, we still need one extra change to guarantee that dst != tmp, which we can do with a TEMP_DEF effect for dst. I tried adding this extra change and it seems to work.
> 
> EDIT: My local `hotspot:tier1` passed with fastdebug build on SG2042.
> 
> ```
> @@ -8936,7 +8941,7 @@ instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
>  instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
>    match(Set dst (DecodeNKlass src));
> 
> -  effect(TEMP tmp);
> +  effect(TEMP_DEF dst, TEMP tmp);
> 
>    ins_cost(ALU_COST);
>    format %{ "decode_klass_not_null  $dst, $src\t#@decodeKlass_not_null" %}
> ```

In this sense, we're not saving one register (t0), as we require extra register by `effect(TEMP_DEF dst, TEMP tmp);`, right?

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PR Comment: https://git.openjdk.org/jdk/pull/27138#issuecomment-3270918249