RFR: 8367066: RISC-V: refine register selection in MacroAssembler:: decode_klass_not_null [v2]

[Fei Yang]

On Tue, 9 Sep 2025 14:13:16 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Hi,
>> Can you help to review this patch?
>> 
>> Previously, the register selection in MacroAssembler:: decode_klass_not_null is misleading, better to refine it to improve the readability.
>> 
>> Thanks!
>> 
>> Running runtime test tier1/2/3...
>
> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
> 
>   refine

Marked as reviewed by fyang (Reviewer).

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3423:

> 3421:   if (CompressedKlassPointers::shift() != 0) {
> 3422:     // dst = (src << shift) + xbase
> 3423:     shadd(dst, src, xbase, dst /* temporary, dst != xbase */, CompressedKlassPointers::shift());

Is it safer to turn the code comment into an assertion? It will trigger if people incorrectly sets `xbase`.

assert_different_registers(dst, xbase);
// dst = (src << shift) + xbase
shadd(dst, src, xbase, dst, CompressedKlassPointers::shift());

-------------

PR Review: https://git.openjdk.org/jdk/pull/27138#pullrequestreview-3203851463
PR Review Comment: https://git.openjdk.org/jdk/pull/27138#discussion_r2335153299