RFR: 8367066: RISC-V: refine register selection in MacroAssembler:: decode_klass_not_null [v2]

[Hamlin Li]

On Wed, 10 Sep 2025 00:24:53 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   refine
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3423:
> 
>> 3421:   if (CompressedKlassPointers::shift() != 0) {
>> 3422:     // dst = (src << shift) + xbase
>> 3423:     shadd(dst, src, xbase, dst /* temporary, dst != xbase */, CompressedKlassPointers::shift());
> 
> Is it safer to turn the code comment into an assertion? It will trigger if people incorrectly sets `xbase`.
> 
> assert_different_registers(dst, xbase);
> // dst = (src << shift) + xbase
> shadd(dst, src, xbase, dst, CompressedKlassPointers::shift());

In `shadd` when `tmp` (here we use dst as tmp) is used, there is already an assert there.

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PR Review Comment: https://git.openjdk.org/jdk/pull/27138#discussion_r2335956852