RFR: 8367692: RISC-V: Align post call nop

[Robbin Ehn]

On Wed, 24 Sep 2025 15:20:15 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hi please, consider.
>> 
>> As ziccif require instructions to natural aligned to be atomic the 4 byte post call nop must be aligned.
>> But I don't want to add a c.nop(2b) to align the nop(4b) which means the jal(r) must also be algined.
>> As we have no utility to aligned the end of an instruction sequence the call it self is aligned and uses only 4 byte instructions. Only in the case where we could use an two c-instruction we may loose space.
>> 
>> Thanks, Robbin
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 359:
> 
>> 357: void MacroAssembler::post_call_nop() {
>> 358:   assert(!in_compressible_scope(), "Must be");
>> 359:   assert_alignment(pc());
> 
> Does the first assertion make sense here? Seems to me the second one will just suffice.

The code today to avoid C-instructions by:
- We do not have nop -> c.nop conversion.
- We use zr as destination

Instead of relying of this 'trickery', I'm saying these instructions are not c-compressed and user have to turn them off before calling here.
I.e. now this code will work with nop->c.nop conversion and using another register in the li32. (which is very sneaky way to get 4 byte instructions)

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PR Review Comment: https://git.openjdk.org/jdk/pull/27467#discussion_r2378047246