RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads [v4]

[Andrew Haley]

On Wed, 19 Nov 2025 12:47:18 GMT, Samuel Chee <duke at openjdk.org> wrote:

>> Replaces the DMB ISH + LD + DMB ISHLD sequence with LDAR for volatile field loads - for example, AtomicLong::get.
>> 
>> This is valid, as originally the DMBs were necessary due to the case described here - https://bugs.openjdk.org/browse/JDK-8179954. As in the rare case where the LD can be reordered with an LDAR or STLR from the C2 implementation for stores and loads, these DMBs are required.
>> However, acquire/release operations use a sequentially consistent model which does not allow reordering between them. Hence, the LD can be replaced with an LDAR to disallow reordering with a STLR/LDAR and the first DMB can be removed.
>> 
>> The LDAR has acquire semantics, so it's impossible for memory accesses after to be reordered before; the DMB ISHLD is not required. Therefore, a singular LDAR is sufficient.
>
> Samuel Chee has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Rename load_generic -> load_relaxed

src/hotspot/cpu/riscv/c1_LIRGenerator_riscv.cpp line 1176:

> 1174:                                        CodeEmitInfo* info) {
> 1175:   __ volatile_load_mem_reg(address, result, info);
> 1176:   return true;

Suggestion:

void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
                                       CodeEmitInfo* info) {
  __ volatile_load_mem_reg(address, result, info);
  __ membar_acquire();
}

Reason: this stuff belongs in the CPU-specfic code.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26748#discussion_r2787623134