RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads [v4]

[Ruben]

On Tue, 10 Feb 2026 12:16:52 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Samuel Chee has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Rename load_generic -> load_relaxed
>
> src/hotspot/cpu/riscv/c1_LIRGenerator_riscv.cpp line 1176:
> 
>> 1174:                                        CodeEmitInfo* info) {
>> 1175:   __ volatile_load_mem_reg(address, result, info);
>> 1176:   return true;
> 
> Suggestion:
> 
> void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
>                                        CodeEmitInfo* info) {
>   __ volatile_load_mem_reg(address, result, info);
>   __ membar_acquire();
> }
> 
> Reason: this stuff belongs in the CPU-specfic code.

This would add the `membar_acquire` where in case of `needs_atomic && !is_volatile` in `BarrierSetC1::load_at_resolved` it would have been skipped. To mitigate this would it be suitable to add a `needs_acquire` parameter to `volatile_field_load`?

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PR Review Comment: https://git.openjdk.org/jdk/pull/26748#discussion_r2866616099