RFR: 8376167: RISC-V: Fix redundant zext.w in macroAssembler_riscv.cpp

[pure]

The RISC-V addiw instruction includes built-in sign extension. When the 32-bit immediate value is 0, no sign extension is needed. The current JIT assembler generates a redundant zext.w instruction.

0x0000002aac9e9ce8:   lui     t3,0x95010                  ; {metadata('java/lang/Long')}
0x0000002aac9e9cec:   addiw   t3,t3,-1136
0x0000002aac9e9cf0:   zext.w  t3,t3
0x0000002aac9e9cf4:   beq     t2,t3,0x0000002aac9e9cfc

So, in macroAssembler_riscv.cpp source code, we can add the additional judgment to avoid the zext instruction

-------------

Commit messages:
 - 8376167: RISC-V: Fix redundant zext.w in macroAssembler_riscv.cpp

Changes: https://git.openjdk.org/jdk/pull/29683/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=29683&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8376167
  Stats: 8 lines in 1 file changed: 7 ins; 0 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/29683.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/29683/head:pull/29683

PR: https://git.openjdk.org/jdk/pull/29683