RFR: 8376167: RISC-V: Fix redundant zext.w in macroAssembler_riscv.cpp

[Fei Yang]

On Thu, 12 Feb 2026 03:10:22 GMT, pure <duke at openjdk.org> wrote:

> The RISC-V addiw instruction includes built-in sign extension. When the 32-bit immediate value is 0, no sign extension is needed. The current JIT assembler generates a redundant zext.w instruction.
> 
> 0x0000002aac9e9ce8:   lui     t3,0x95010                  ; {metadata('java/lang/Long')}
> 0x0000002aac9e9cec:   addiw   t3,t3,-1136
> 0x0000002aac9e9cf0:   zext.w  t3,t3
> 0x0000002aac9e9cf4:   beq     t2,t3,0x0000002aac9e9cfc
> 
> So, in macroAssembler_riscv.cpp source code, we can add the additional judgment to avoid the zext instruction

@bbit9 : Hi, I will have a look. Can you enable GHA on your fork?

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PR Comment: https://git.openjdk.org/jdk/pull/29683#issuecomment-3888554395