RFR: 8378675: PPC64: increase instruction cache line size [v3]

[Martin Doerr]

On Fri, 27 Feb 2026 14:34:49 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>> src/hotspot/cpu/ppc/vm_version_ppc.cpp line 535:
>> 
>>> 533:   _L1_data_cache_line_size = os::get_dcache_line_size();
>>> 534:   assert(_L1_data_cache_line_size >= DEFAULT_CACHE_LINE_SIZE,
>>> 535:          "processors with smaller cache line size are no longer supported");
>> 
>> It worries me a little bit that if `_L1_data_cache_line_size` is too big then `MacroAssembler::clear_memory_doubleword()` can fail to clear all bytes.
>> I guess I shouldn't be that paranoid.
>
> We definitely need the correct value. If it's too small, we may clear memory beyond the end. All supported processors use a size of 128 Bytes. We could even assert that (I'm not requesting this).

The ISA document seems to suggest using OS functions:
"It is suggested that the operating system provide a service that allows an application program to obtain the following information.
...
7. Instruction cache block size
8. Data cache block size"

On linux, it would also be possible to use the information from files which exist for each processor and cache: /sys/devices/system/cpu/cpu0/cache/index0, but that is more tricky.

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PR Review Comment: https://git.openjdk.org/jdk/pull/29918#discussion_r2864687443