RFR: 8378675: PPC64: increase instruction cache line size [v3]

[Martin Doerr]

On Fri, 27 Feb 2026 13:32:32 GMT, Richard Reingruber <rrich at openjdk.org> wrote:

>> David Briemann has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   remove comments, fix comparison
>
> src/hotspot/cpu/ppc/vm_version_ppc.cpp line 535:
> 
>> 533:   _L1_data_cache_line_size = os::get_dcache_line_size();
>> 534:   assert(_L1_data_cache_line_size >= DEFAULT_CACHE_LINE_SIZE,
>> 535:          "processors with smaller cache line size are no longer supported");
> 
> It worries me a little bit that if `_L1_data_cache_line_size` is too big then `MacroAssembler::clear_memory_doubleword()` can fail to clear all bytes.
> I guess I shouldn't be that paranoid.

We definitely need the correct value. If it's too small, we may clear memory beyond the end. All supported processors use a size of 128 Bytes. We could even assert that (I'm not requesting this).

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PR Review Comment: https://git.openjdk.org/jdk/pull/29918#discussion_r2864631439