[jdk17u-dev] RFR: 8265263: AArch64: Combine vneg with right shift count

[Hao Sun]

On Thu, 20 Oct 2022 09:08:36 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_neon.ad line 4254:
>> 
>>> 4252: instruct vslcnt8B(vecD dst, iRegIorL2I cnt) %{
>>> 4253:   predicate(n->as_Vector()->length_in_bytes() == 4 ||
>>> 4254:                             n->as_Vector()->length_in_bytes() == 8);
>> 
>> We may improve the style here, i.e. removing the leading whitespace.
>
> Not in a backport.

I see. Thanks for your comment.

>> src/hotspot/cpu/aarch64/aarch64_neon.ad line 4276:
>> 
>>> 4274: 
>>> 4275: instruct vsrcnt8B(vecD dst, iRegIorL2I cnt) %{
>>> 4276:   predicate(UseSVE == 0 && (n->as_Vector()->length_in_bytes() == 4 ||
>> 
>> As mentioned in the commit msg, I think `UseSVE == 0` check is not needed here.
>
> Again, the place to fix that is JDK head.

But `UseSVE == 0` check is removed for `vslcnt8B` and `vslcnt16B` already.
As stated in the commit msg, VectorAPI  SVE codegen part is missing for 17u.

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PR: https://git.openjdk.org/jdk17u-dev/pull/811