[jdk21u] Integrated: 8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock

[Gui Cao]

On Fri, 24 Nov 2023 02:22:27 GMT, Gui Cao <gcao at openjdk.org> wrote:

> Clean backport which fixes a potential risk for passing t0 as temporary register to MacroAssembler::lightweight_lock/unlock. This is a riscv-specific change, risk is low.
> 
> ### Testing:
> - [x]  Run tier1-3 tests with qemu 8.1.50 (default locking mode) (release)
> - [x]  Run non-trivial benchmark workloads (specjbb2005, dacapo, renaissance) with -XX:LockingMode=2 (fastdebug & release)

This pull request has now been integrated.

Changeset: 3df010f4
Author:    Gui Cao <gcao at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk21u/commit/3df010f444428ecc5ac1efae569dd92134bdf207
Stats:     52 lines in 10 files changed: 9 ins; 0 del; 43 mod

8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock

Backport-of: a6098e438d7c5aa458b37bf94a9cfe706da35d52

-------------

PR: https://git.openjdk.org/jdk21u/pull/399