RFR: RISC-V: Avoid return misprediction

[Robbin Ehn]

On Mon, 21 Oct 2024 02:54:40 GMT, Fei Yang <fyang at openjdk.org> wrote:

> This is a small enhancement for the loom riscv-specifc changes. This fixes a return misprediction performance issue which was recently discovered. See https://github.com/openjdk/jdk/pull/21406 for more details. It simply changes usage of scratch registers prefering `t1` instead of `t0` for jumps and calls, which should not affect basic functionality. This also reverted an unnecessary change previously made in two files  `src/hotspot/cpu/riscv/c2_CodeStubs_riscv.cpp` and `src/hotspot/cpu/riscv/templateTable_riscv.cpp`.
> 
> Testing performed on linux-riscv64:
> - [x] make test TEST="hotspot_loom jdk_loom" (release build)
> - [x] make test TEST="hotspot_loom jdk_loom" TEST_VM_OPTS="-XX:+VerifyStack -XX:+VerifyContinuations" (fastdebug build)

@RealFYang
I programmically looked for t1 uses in Nodes.
The only ones I found missing **cr** (set or kill) was ForwardExceptionjmp and RethrowException.
But compiler don't expect **cr** to survival these i.e. x86 do not kill **cr** in those cases.
Note, maybe some Node(s) was never created, so this is not 100% complete check, but 99%.

@luhenry thanks!

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PR Comment: https://git.openjdk.org/loom/pull/215#issuecomment-2425702075