[vectorIntrinsics+mask] RFR: 8265109: SVE predicate register allocation support for vectorIntrinsics

[Jatin Bhateja]

On Wed, 14 Apr 2021 01:00:52 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

>> This is the SVE predicate register allocation part for Vector API masking support. Since we don't have sufficent usages to test it in
>> jdk/jdk, and based on @sviswa7 's proposal [1], we would like to put it to vectorIntrinsics+mask first and get tested here with further predicate-based vector masking support, though so far no issue found with Xiaohong's initial Vector API masking support.
>> 
>> [1] https://mail.openjdk.java.net/pipermail/panama-dev/2021-April/012920.html
>
> src/hotspot/share/adlc/formssel.cpp line 2278:
> 
>> 2276:   if (strcmp(name, "RegL") == 0) size = 2;
>> 2277:   if (strcmp(name, "RegN") == 0) size = 1;
>> 2278:   if (strcmp(name, "RegVectMask") == 0) size = 1;
> 
> This might not work across architectures. @jatin-bhateja what are your thoughts on this?

It doesn't have much usage apart from semantic checking for bound registers. 
But for correct ness a bounded opmask reg class for x86 has two registers.
Could not locate bounded reg class definitions for SVE predicate registers in aarch64.ad

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PR: https://git.openjdk.java.net/panama-vector/pull/65