[vectorIntrinsics+mask] RFR: 8265109: SVE predicate register allocation support for vectorIntrinsics

[Ningsheng Jian]

On Thu, 15 Apr 2021 03:14:10 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> src/hotspot/share/adlc/formssel.cpp line 2278:
>> 
>>> 2276:   if (strcmp(name, "RegL") == 0) size = 2;
>>> 2277:   if (strcmp(name, "RegN") == 0) size = 1;
>>> 2278:   if (strcmp(name, "RegVectMask") == 0) size = 1;
>> 
>> This might not work across architectures. @jatin-bhateja what are your thoughts on this?
>
> It doesn't have much usage apart from semantic checking for bound registers. 
> But for correct ness a bounded opmask reg class for x86 has two registers.
> Could not locate bounded reg class definitions for SVE predicate registers in aarch64.ad

Yes, aarch64 does not need this for now. I can either revert this change (leaving it to you for future update if required) or update to size 2 for x86. Which do you prefer?

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PR: https://git.openjdk.java.net/panama-vector/pull/65