[vectorIntrinsics+mask] RFR: 8265109: SVE predicate register allocation support for vectorIntrinsics

[Jatin Bhateja]

On Thu, 15 Apr 2021 04:18:36 GMT, Ningsheng Jian <njian at openjdk.org> wrote:

>> It doesn't have much usage apart from semantic checking for bound registers. 
>> But for correct ness a bounded opmask reg class for x86 has two registers.
>> Could not locate bounded reg class definitions for SVE predicate registers in aarch64.ad
>
> Yes, aarch64 does not need this for now. I can either revert this change (leaving it to you for future update if required) or update to size 2 for x86. Which do you prefer?

I can see ADLC does parse the preprocessors in source sections, by adding a new #define SVE_ENABLE  1 in aarch64_sve.ad  and checking for the same similar to following handling may allow us to set size = 1 for SVE else 2.
https://github.com/openjdk/jdk/blob/master/src/hotspot/share/adlc/formssel.cpp#L2279

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PR: https://git.openjdk.java.net/panama-vector/pull/65