[vectorIntrinsics] RFR: 8261108: Add cast nodes from integer types to float types implementation for Arm SVE [v2]

[Ningsheng Jian]

On Fri, 19 Feb 2021 03:18:04 GMT, Wang Huang <whuang at openjdk.org> wrote:

>> Add the backend codegen for nodes like castb2f / castb2d / casts2f / casts2d / casti2f / casti2d / castl2f / castl2d.
>> 
>> * add `sve_scvtf`  ( and `sve_ucvtf`) encoding
>> * add mock for these instructions
>> * add `VECTOR_CAST_I2F_EXTEND[N]` and `VECTOR_CAST_I2F`
>> 
>> Thank you for your review.
>
> Wang Huang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fix some bugs

src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 3385:

> 3383:     pgrf(Pg, 10), rf(Zn, 5), rf(Zd, 0);                                 \
> 3384:     encode_cvtf_T(T_dst, T_src);                                        \
> 3385:     f(T_dst, 23, 22), f(T_src, 18, 17);                                 \

I would suggest to fill the bits in order, i.e. move f(T_dst, 23, 22) right after (... 31, 24), and then (21, 19), (18, 17)...

src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 3371:

> 3369:     } else if (T_dst == D && T_src == S) {
> 3370:       T_dst = D;
> 3371:       T_src = B;

This looks confusing. I understand that it's just 0b00, but using B here is really confusing. Maybe using 0b00 and 0b11 directly to align with Arm ARM opc/opc2?

-------------

PR: https://git.openjdk.java.net/panama-vector/pull/37