[vectorIntrinsics+mask] RFR: 8274236: Cleanups related to X86 masking support. [v2]

[Jatin Bhateja]

On Thu, 23 Sep 2021 22:51:39 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

>> Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   8274236: Review comments resolved.
>
> src/hotspot/cpu/x86/x86.ad line 1498:
> 
>> 1496:     case Op_VectorStoreMask:
>> 1497:     case Op_VectorBlend:
>> 1498:       if (UseSSE < 3) {
> 
> This doesnt look correct. packusdw needs SSE4.  Also all the others in this case block need SSE4.

Thanks, DONE

> src/hotspot/cpu/x86/x86.ad line 7925:
> 
>> 7923:   predicate(Matcher::vector_length(n) <= 16 && n->in(1)->bottom_type()->isa_vectmask() == NULL);
>> 7924:   match(Set dst (VectorStoreMask src size));
>> 7925:   effect(TEMP_DEF dst);
> 
> The original storeMask2B didn't need TEMP dst and so was a separate rule.

TEMP_DST ensures creation of separate machine operands which gets allocated same register as DST, thus preventing any accidental sharing of register with any other temporary machine operand over the node.  In this case since there is no other explicit temporary register used to effectively, TEMP_DEF  is same at DEF for all practical purpose.

> src/hotspot/cpu/x86/x86.ad line 7948:
> 
>> 7946:   match(Set dst (VectorStoreMask src size));
>> 7947:   format %{ "vector_store_mask $dst, $src \t! elem size is $size byte[s]" %}
>> 7948:   effect(TEMP_DEF dst);
> 
> The original storeMask4B didn't need TEMP dst and so was a separate rule.

TEMP_DST ensures creation of separate machine operands which gets allocated same register as DST, thus preventing any accidental sharing of register with any other temporary machine operand over the node.  In this case since there is no other explicit temporary register used to effectively, TEMP_DEF  is same at DEF for all practical purpose.

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PR: https://git.openjdk.java.net/panama-vector/pull/131