[vectorIntrinsics] RFR: 8283413: Add C2 mid-end and x86 back-end implementation for bit REVERSE and REVERSE_BYTES operation [v3]

[Jatin Bhateja]

On Thu, 24 Mar 2022 08:37:15 GMT, Quan Anh Mai <duke at openjdk.java.net> wrote:

>> Jatin Bhateja has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains five commits:
>> 
>>  - 8283413: White space removal.
>>  - 8283413: Review comments resoultion, ReverseBytes IR and x86 backend support.
>>  - Merge branch 'vectorIntrinsics' of http://github.com/openjdk/panama-vector into JDK-8283413
>>  - 8283413: Adding Ideal transform for (ReverseV (ReverseV VEC)) => VEC and (ReverseV (ReverseV VEC MASK) MASK)) => VEC
>>  - 8283413: Add C2 mid-end and x86 back-end implementation for bit REVERSE operation
>
> src/hotspot/cpu/x86/x86.ad line 8997:
> 
>> 8995: 
>> 8996: instruct vreverse_reg_evex(vec dst, vec src, vec xtmp1, vec xtmp2, rRegI rtmp) %{
>> 8997:   predicate((VM_Version::supports_avx512bw() || Matcher::vector_length_in_bytes(n) == 64) && !VM_Version::supports_gfni());
> 
> If vector length < 64 we need avx512vl here. I think this and the above should be `VM_Version::supports_avx512vlbw()` instead

Even though there is no X86 target which supports BW but not VL,  but we still need to be granular in emitting correct predications since one can always configure VMs to enable selective target features.

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PR: https://git.openjdk.java.net/panama-vector/pull/182