[vectorIntrinsics+fp16] RFR: 8305563: [vectorapi]: Initial aarch64 backend implementation for FP16 operations

[Andrew Haley]

On Mon, 26 Jun 2023 12:34:12 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

> This patch adds aarch64 (Neon and SVE) backend implementation for the following FP16 operations for which C2 support was added in the commit https://github.com/openjdk/panama-vector/commit/7460d9327aac7d1d2ba6aed4e7137a417dbf6a97 -
> 
> Unary operations : AbsVHF, NegVHF
> Binary operations : AddVHF, SubVHF, MulVHF, DivVHF
> Ternary operations : AddReductionVHF, FmaVHF
> Conversion operations : VectorCastHF2D, VectorCastD2HF
> 
> Some of these operations on Neon machines, require features "fphp" and "asimdhp" to be available. Feature detection for these features have also been added.

src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 2730:

> 2728:     f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23);                \
> 2729:     f(op22, 22); f(op21, 21), rf(Vm, 16), f(op15, 15, 14), f(op3, 13, 10), rf(Vn, 5);       \
> 2730:     rf(Vd, 0);                                                                              \

This is a bit too big for an inline function. Please consider taking the body of this asm and putting it into assembler_aarch64.cpp. See `Assembler::add_sub_immediate` for an example of how this should be done.

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PR Review Comment: https://git.openjdk.org/panama-vector/pull/217#discussion_r1242195930