[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order

[Xiaolin Zheng]

This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

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Commit messages:
 - Fix store condition: instruction has wrong operand order

Changes: https://git.openjdk.java.net/riscv-port/pull/19/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=19&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8278033
  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/19.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/19/head:pull/19

PR: https://git.openjdk.java.net/riscv-port/pull/19