[riscv-port] RFR: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order

[Fei Yang]

On Wed, 1 Dec 2021 02:40:31 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

Looks good and trivial. Thanks.

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Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/19