[riscv-port] RFR: 8278337: riscv: remove unnecessary ld/sd zr around calls [v2]

[kuaiwei]

On Wed, 8 Dec 2021 08:32:18 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> kuaiwei has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 958:
>
>> 956:   int count = 0;
>> 957:   // Zr and sp (x0, x2) should not be pushed
>> 958:   assert((bitset & 0b101) == 0, "zr or sp is in bitset: %x", bitset);
>
> I don't think we need this assertion here. Function bitset_to_regs should not care about specific registers in the set.

Removed as comment. Thanks.

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 983:
>
>> 981:   }
>> 982:   for (int i = count - 1; i >= 0; i--) {
>> 983:     sd(as_Register(regs[i]), Address(stack, (count -1 - i) * wordSize + offset));
>
> whitespace is missing here. Should be: (count - 1 - i)

Fixed.

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PR: https://git.openjdk.java.net/riscv-port/pull/25