[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers

[Yadong Wang]

On Wed, 15 Dec 2021 02:59:37 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> Hi team,
> 
> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
> 
> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
> 
> Thanks,
> Xiaolin

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 289:

> 287:   __ block_comment("save_live_registers");
> 288: 
> 289:   // if the number of pushed regs is odd, zr will be added

`// if the number of pushed regs is odd, zr will be added` is out-of-date after JDK-8278337.

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 352:

> 350:   }
> 351: 
> 352:   // we save x0, x5 ~ x31, except x1, x2, x3, x4

Are we still saving x0 now?

src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 198:

> 196:   for (int i = 5; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
> 197:     Register r = as_Register(i);
> 198:     if (r != xthread && r != t0 && r != t1) {

Why not start the loop from x7?

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PR: https://git.openjdk.java.net/riscv-port/pull/31