[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2]
Xiaolin Zheng
xlinzheng at openjdk.java.net
Wed Dec 15 09:02:06 UTC 2021
On Wed, 15 Dec 2021 03:11:21 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:
>> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
>>
>> Fix comments for JDK-8278337 and commit other improvements as proposed
>
> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 289:
>
>> 287: __ block_comment("save_live_registers");
>> 288:
>> 289: // if the number of pushed regs is odd, zr will be added
>
> `// if the number of pushed regs is odd, zr will be added` is out-of-date after JDK-8278337.
Right -- changed.
> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 352:
>
>> 350: }
>> 351:
>> 352: // we save x0, x5 ~ x31, except x1, x2, x3, x4
>
> Are we still saving x0 now?
Right -- changed.
> src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 198:
>
>> 196: for (int i = 5; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
>> 197: Register r = as_Register(i);
>> 198: if (r != xthread && r != t0 && r != t1) {
>
> Why not start the loop from x7?
Thanks for the nice reminder -- changed.
-------------
PR: https://git.openjdk.java.net/riscv-port/pull/31
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