[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2]

[Feilong Jiang]

On Wed, 15 Dec 2021 09:02:03 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> x3 is the global pointer register used to reference global variables in C++ code, generated by linker; and x4 is the thread pointer register and would be modified by the kernel. In the riscv-port repo, we have no other modifications for the x3 & x4 registers so I would recommend removing the x3 & x4 saving logic in register savers. Previously verified along with other patches under full tiers jdk/hotspot on boards, and verified a simple `test/jtreg/hotspot/compiler` after fixing conflicts with [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25).
>> 
>> BTW since we remove both two registers together, sp remains 16-byte aligned without other changes in stack frames.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix comments for JDK-8278337 and commit other improvements as proposed

src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 337:

> 335:   // if the number of popped regs is odd, the reserved slot for alignment will be removed
> 336:   // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4) & x10
> 337:   __ pop_reg(RegSet::range(x5, x9), sp);   // pop zr, x5 ~ x9

Is `zr` will be poped?

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PR: https://git.openjdk.java.net/riscv-port/pull/31