[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2]

[Xiaolin Zheng]

On Thu, 16 Dec 2021 01:17:40 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix comments for JDK-8278337 and commit other improvements as proposed
>
> src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp line 337:
> 
>> 335:   // if the number of popped regs is odd, the reserved slot for alignment will be removed
>> 336:   // integer registers except ra(x1) & sp(x2) & gp(x3) & tp(x4) & x10
>> 337:   __ pop_reg(RegSet::range(x5, x9), sp);   // pop zr, x5 ~ x9
> 
> Is `zr` will be poped?

Currently it seems not: it looks like [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25) only removes the zr saving and restoring logic, but just remains that stack slot originally for zr unchanged.

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PR: https://git.openjdk.java.net/riscv-port/pull/31