[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2]

[Xiaolin Zheng]

On Thu, 16 Dec 2021 01:49:25 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Currently it seems not: it looks like [JDK-8278337](https://github.com/openjdk/riscv-port/pull/25) only removes the zr saving and restoring logic, but just remains that stack slot originally for zr unchanged.
>
> comment should be updated too though.

Thanks for pointing it out -- seems there are unfixed comments at large out of my sight. I have fixed them according to the assembly code.

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PR: https://git.openjdk.java.net/riscv-port/pull/31