[riscv-port] RFR: 8278644: riscv: Intrinsify mulAdd [v2]

[Feilong Jiang]

> BigInteger intrinsic: mulAdd intrinsic is missed in current vm. It should be implemented.
> The JMH test of mulAdd intrinsic on the matched board shows that the performance can be improved by 0.69%~21.91% when the length of BigInteger changed from 1 to 5000, compared with that of C2.
> JMH test: [MyBenchmark.java](https://bugs.openjdk.java.net/secure/attachment/97414/MyBenchmark.java)
> 
> Performed full jtreg test with qemu without new failures.
> 
> Results list as follows
> | length | intrinsic(ops/ms) | no intrinsic(ops/ms) | intrinsic / no intrinsic |
> | ------ | ------ | ------ | ------ | 
> | 1 | 1643.111 | 1623.814 | 1.18% |
> | 2 | 1597.927 | 1585.216 | 0.80% |
> | 3 | 1542.249 | 1502.455 | 2.65% |
> | 5 | 1533.371 | 1522.837 | 0.69% |
> | 10 | 1377.683 | 1361.718 | 1.17% |
> | 50 | 925.826 | 844.276 | 9.62% |
> | 100 | 638.767 | 576.276 | 10.84% |
> | 1000 | 99.870 | 84.796 | 17.78% |
> | 2000 | 51.511 | 43.624 | 18.08% |
> | 5000 | 18.017 | 14.779 | 21.91% |

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  change the type of i in for loop to match the type of unroll

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/36/files
  - new: https://git.openjdk.java.net/riscv-port/pull/36/files/90816db0..620dcde8

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=36&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=36&range=00-01

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/36.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/36/head:pull/36

PR: https://git.openjdk.java.net/riscv-port/pull/36