felix.yang at huawei.com
Sat Nov 6 02:30:00 UTC 2021
The RISC-V Port Project has been recorded in the OpenJDK Census .
We already have the repo  and the mailing list (pre-populated with initial Reviewers) .
The "master" branch is seeded with the most recent gh:openjdk/jdk and will automatically be sync'd to that repo.
I will push a new "riscv-port" branch to the Project repo. Future Project development should happen on this new branch.
We also have a web page  and a wikispace .
Note that the wikispace is still being setup, and we need to wait for write access permission.
I'll add something more on the wiki page once it's ready for editing.
The next thing for me to do is to propose the current code from the riscv-port-branch of jdk-sandbox
as GitHub Pull-Request. This course made things simpler from the legal point of view.
It would be beneficial to track our future issues in JBS. I will ask ops to add "riscv" as a CPU target.
Like other Projects, we also need project-specific entries for the Affected and Fix Version fields, e.g. JDK-8251041 .
I think we can do the same.
Aleksey Shipilev is building nightlies here . And we've provided build instructions for reference .
You can try the RISC-V JDK with QEMU User/System mode or HiFive Unleashed/Unmatched board.
Have fun and happy hacking!
More information about the riscv-port-dev