November 2021 Archives by author

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Starting: Sat Nov 6 02:30:00 UTC 2021
Ending: Tue Nov 30 13:29:29 UTC 2021
Messages: 98

Welcome announcement Yangfei (Felix)
Welcome announcement Yangfei (Felix)
[riscv-port] RFR: 8276792: RISC-V Port: Initial support for RV64GV Aleksey Shipilev
Welcome announcement Aleksey Shipilev
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register Aleksey Shipilev
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 Aleksey Shipilev
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental Yadong Wang
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental Yadong Wang
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental [v2] Yadong Wang
[riscv-port] RFR: 8277430: riscv: Refactor interpreter native wrappers Yadong Wang
[riscv-port] RFR: 8277430: riscv: Refactor interpreter native wrappers [v2] Yadong Wang
[riscv-port] Integrated: 8277430: riscv: Refactor interpreter native wrappers Yadong Wang
[riscv-port] RFR: 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2 Yadong Wang
[riscv-port] RFR: 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2 Yadong Wang
[riscv-port] Integrated: 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2 Yadong Wang
[riscv-port] RFR: 8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership check Yadong Wang
[riscv-port] Integrated: 8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership check Yadong Wang
[riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate Yadong Wang
[riscv-port] Integrated: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate Yadong Wang
[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2] Yadong Wang
[riscv-port] RFR: 8276792: RISC-V Port: Initial support for RV64GV Fei Yang
[riscv-port] Integrated: 8276792: RISC-V Port: Initial support for RV64GV Fei Yang
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 Fei Yang
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register Fei Yang
[riscv-port] Withdrawn: 8276988: riscv: Fix a register name string: lr to x5 Fei Yang
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 Fei Yang
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register Fei Yang
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register Fei Yang
[riscv-port] RFR: 8277167: riscv: Remove unnecessary register declaration for lr Fei Yang
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux Fei Yang
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.ie Fei Yang
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux [v2] Fei Yang
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux [v3] Fei Yang
[riscv-port] RFR: 8277392: riscv: Port missing trampoline logic from AArch64 platform Fei Yang
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental [v2] Fei Yang
[riscv-port] RFR: 8277430: riscv: Refactor interpreter native wrappers Fei Yang
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.gd [v2] Fei Yang
[riscv-port] RFR: 8277430: riscv: Refactor interpreter native wrappers [v2] Fei Yang
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.gd [v2] Fei Yang
[riscv-port] RFR: 8277391: riscv: Remove the USE_LIBRARY_BASED_TLS_ONLY macro to use tls instead of pthread_getspecific [v2] Fei Yang
[riscv-port] RFR: 8277391: riscv: Remove the USE_LIBRARY_BASED_TLS_ONLY macro to use tls instead of pthread_getspecific [v3] Fei Yang
[riscv-port] RFR: 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2 Fei Yang
[riscv-port] RFR: 8277431: riscv: Intrinsify recursive ObjectMonitor locking for C2 Fei Yang
[riscv-port] RFR: 8277877: C2 fast_unlock intrinsic on riscv has unnecessary ownership check Fei Yang
[riscv-port] RFR: 8277884: riscv: Fix cmpxchg_narrow_value that needs to sign-extend non-bool results Fei Yang
[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate Fei Yang
[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate [v2] Fei Yang
[riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate Fei Yang
[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2] Fei Yang
[riscv-port] RFR: 8277167: riscv: Remove unnecessary register declaration for lr Yanhong Zhu
[riscv-port] Integrated: 8277167: riscv: Remove unnecessary register declaration for lr Yanhong Zhu
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux Yanhong Zhu
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux [v2] Yanhong Zhu
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux [v3] Yanhong Zhu
[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux [v3] Yanhong Zhu
[riscv-port] Integrated: 8277036: riscv: Get CPU features from the auxiliary vector on Linux Yanhong Zhu
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental Yanhong Zhu
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental Yanhong Zhu
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental [v2] Yanhong Zhu
[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental [v2] Yanhong Zhu
[riscv-port] Integrated: 8277440: riscv: Move UseVExt from product to experimental Yanhong Zhu
git: openjdk/riscv-port: riscv-port: Adjust jcheck config for RISC-V Port duke
git: openjdk/riscv-port: riscv-port: 107 new changesets duke
git: openjdk/riscv-port: riscv-port: 85 new changesets duke
git: openjdk/riscv-port: riscv-port: 61 new changesets duke
git: openjdk/riscv-port: riscv-port: 13 new changesets duke
[riscv-port] RFR: 8277968: riscv: detect vector extension with vcsr kuaiwei
[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2] kuaiwei
[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2] kuaiwei
New candidate JEP: 422: Linux/RISC-V Port mark.reinhold at oracle.com
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register zhengxiaolinX
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 zhengxiaolinX
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 zhengxiaolinX
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register zhengxiaolinX
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 zhengxiaolinX
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 zhengxiaolinX
[riscv-port] RFR: 8276989: riscv: C1 should not allocate x3, which is the gp register zhengxiaolinX
[riscv-port] RFR: 8276988: riscv: Fix a register name string: lr to x5 zhengxiaolinX
[riscv-port] Integrated: 8276988: riscv: Fix a register name string: lr to x5 zhengxiaolinX
[riscv-port] Integrated: 8276989: riscv: C1 should not allocate x3, which is the gp register zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: Implement tls function MacroAssembler::get_thread() using tls.ie zhengxiaolinX
[riscv-port] RFR: 8277392: riscv: Port missing trampoline logic from AArch64 platform zhengxiaolinX
[riscv-port] Integrated: 8277392: riscv: Port missing trampoline logic from AArch64 platform zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.ie zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.gd [v2] zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.gd [v2] zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: implement tls function MacroAssembler::get_thread() by using tls.gd [v2] zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: Remove the USE_LIBRARY_BASED_TLS_ONLY macro to use tls instead of pthread_getspecific [v3] zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: Remove the USE_LIBRARY_BASED_TLS_ONLY macro to use tls instead of pthread_getspecific [v3] zhengxiaolinX
[riscv-port] RFR: 8277391: riscv: Remove the USE_LIBRARY_BASED_TLS_ONLY macro to use tls instead of pthread_getspecific [v3] zhengxiaolinX
[riscv-port] Integrated: 8277391: riscv: Remove the USE_LIBRARY_BASED_TLS_ONLY macro to use tls instead of pthread_getspecific zhengxiaolinX
[riscv-port] RFR: 8277884: riscv: Fix cmpxchg_narrow_value that needs to sign-extend non-bool results zhengxiaolinX
[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate zhengxiaolinX
[riscv-port] RFR: 8277884: riscv: Fix cmpxchg_narrow_value that needs to sign-extend non-bool results zhengxiaolinX
[riscv-port] Integrated: 8277884: riscv: Fix cmpxchg_narrow_value that needs to sign-extend non-bool results zhengxiaolinX
[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate [v2] zhengxiaolinX
[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate [v2] zhengxiaolinX
[riscv-port] Integrated: 8277883: riscv: Fix a temp register usage in eden_allocate zhengxiaolinX

Last message date: Tue Nov 30 13:29:29 UTC 2021
Archived on: Tue Nov 30 13:29:38 UTC 2021

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