[riscv-port] Integrated: 8276792: RISC-V Port: Initial support for RV64GV

[Fei Yang]

On Mon, 8 Nov 2021 03:15:55 GMT, Fei Yang <fyang at openjdk.org> wrote:

> This riscv64 port supports RV64GV, shorthand for RV64IMAFDV ISA extensions, and covers the templateInterpreter, C1 and C2, excluding AOT/JVMCI. All existing GCs are available on riscv64, including ZGC and ShenandoahGC.
> 
> Passed jtreg tier{1,2,3,4} and jcstress tests on HiFive Unmatched board. SPECjbb & SPECjvm benchmark tests are also carried out regularly. So it should be good enough to run most Java programs.

This pull request has now been integrated.

Changeset: 7148c398
Author:    Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/7148c39832fe522bad91df77ef4b5c9371193c35
Stats:     56639 lines in 189 files changed: 56486 ins; 55 del; 98 mod

8276792: RISC-V Port: Initial support for RV64GV

Co-authored-by: Yadong Wang <yadonn.wang at huawei.com>
Co-authored-by: Yanhong Zhu <zhuyanhong2 at huawei.com>
Co-authored-by: Feilong Jiang <jiangfeilong at huawei.com>
Co-authored-by: Kun Wang <wangkun49 at huawei.com>
Co-authored-by: Zhuxuan Ni <nizhuxuan at huawei.com>
Co-authored-by: Taiping Guo <guotaiping1 at huawei.com>
Co-authored-by: Kang He <hekang6 at huawei.com>
Co-authored-by: Aleksey Shipilev <shade at openjdk.org>
Reviewed-by: shade

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PR: https://git.openjdk.java.net/riscv-port/pull/1