[riscv-port] RFR: 8277440: riscv: Move UseVExt from product to experimental [v2]

[Yanhong Zhu]

> Currently, riscv port supports vector operations which is fully compatible with vector extension 1.0 spec. And we have passed tier 1-4 tests with option "-XX:+UseVExt" with QEMU.
> 
> Due to lack of native environment which supports vector extension 1.0, we cannot carry out tests for vector operations on real hardware. So we decided to move port-specific option UseVExt from product to experimental for now, and rename UseVExt to UseRVV.
> 
> This also fixes some typos in comments, and  removes unused v extension instructions.
> 
> The test results on HiFive Unleashed board (rv64imafdc) and NeZha D1 board (rv64imafdcvu) are in line with expectations.

Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:

  Set UseRVV EXPERIMENTAL

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/11/files
  - new: https://git.openjdk.java.net/riscv-port/pull/11/files/829cb59d..5283eec6

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=11&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=11&range=00-01

  Stats: 5 lines in 2 files changed: 0 ins; 4 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/11.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/11/head:pull/11

PR: https://git.openjdk.java.net/riscv-port/pull/11