[riscv-port] Integrated: 8277440: riscv: Move UseVExt from product to experimental

[Yanhong Zhu]

On Fri, 19 Nov 2021 08:36:31 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> Currently, riscv port supports vector operations which is fully compatible with vector extension 1.0 spec. And we have passed tier 1-4 tests with option "-XX:+UseVExt" with QEMU.
> 
> Due to lack of native environment which supports vector extension 1.0, we cannot carry out tests for vector operations on real hardware. So we decided to move port-specific option UseVExt from product to experimental for now, and rename UseVExt to UseRVV.
> 
> This also fixes some typos in comments, and  removes unused v extension instructions.
> 
> The test results on HiFive Unleashed board (rv64imafdc) and NeZha D1 board (rv64imafdcvu) are in line with expectations.

This pull request has now been integrated.

Changeset: dfde4e4e
Author:    Yanhong Zhu <yzhu at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/dfde4e4ebfb1c15f1fb225f7400aced51cc469dd
Stats:     436 lines in 18 files changed: 8 ins; 333 del; 95 mod

8277440: riscv: Move UseVExt from product to experimental

Reviewed-by: yadongwang, fyang

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PR: https://git.openjdk.java.net/riscv-port/pull/11