[riscv-port] RFR: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

[Yadong Wang]

This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:

For the
sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and
SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores,
backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.

It may cause an unspecified behaviour depends on specific hardware implementations.

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Commit messages:
 - 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

Changes: https://git.openjdk.java.net/riscv-port/pull/17/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=17&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8277890
  Stats: 24 lines in 1 file changed: 12 ins; 8 del; 4 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/17.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/17/head:pull/17

PR: https://git.openjdk.java.net/riscv-port/pull/17