CompareAndSet fails intermittently for riscv

[yangfei at iscas.ac.cn]

Hi,

> -----Original Messages-----
> From: "Aleksey Shipilev" <shade at redhat.com>
> Sent Time: 2022-08-25 02:21:54 (Thursday)
> To: yangfei at iscas.ac.cn
> Cc: "wangyadong (E)" <yadonn.wang at huawei.com>, "Vladimir Kempik" <vladimir.kempik at gmail.com>, "riscv-port-dev at openjdk.org" <riscv-port-dev at openjdk.org>
> Subject: Re: CompareAndSet fails intermittently for riscv
> 
> On 8/17/22 04:11, yangfei at iscas.ac.cn wrote:
> > I suspect another jtreg test: test/jdk/java/util/concurrent/atomic/Serial.java also have the same issue.
> > I once reduced this test into [1] and it looks that this will always fail on my unmatched board.
> > But it passes if we disable the intrinsic like:
> >      $ java -XX:+UnlockDiagnosticVMOptions -XX:DisableIntrinsic=_weakCompareAndSetLongRelease Serial
> Whoa, I missed this. This is actually the test bug that manifests on single-threaded RISC-V :P
>    https://mail.openjdk.org/pipermail/riscv-port-dev/2022-August/000594.html

Nice analysis. Suprprised to know it's in fact a bug for such an old test case!

Thanks,
Fei</riscv-port-dev at openjdk.org></vladimir.kempik at gmail.com></yadonn.wang at huawei.com></shade at redhat.com>