[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2]

Yadong Wang yadongwang at openjdk.java.net
Tue Feb 15 06:25:42 UTC 2022

On Tue, 15 Feb 2022 03:57:06 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> Could I have a review of this patch - this is just a trivial refactoring with some cleanups for `nativeInst_riscv.h/cpp` using `Assembler::extract()` with raw bits, by adding `extract_rs1`, `extract_rs2`, `extract_rd`, `extract_opcode`, and `extract_funct3` to make the code cleaner and conciser. Tested hotspot tier1 on Qemu with no other errors found.
>> Thanks,
>> Xiaolin
> Xiaolin Zheng has updated the pull request incrementally with two additional commits since the last revision:
>  - Remove local vars
>  - A little optimization

src/hotspot/cpu/riscv/nativeInst_riscv.hpp line 160:

> 158:     const address addi4 = slli3 + instruction_size;
> 159:     const Register addi4_rs1 = extract_rs1(addi4);
> 160:     const Register addi4_rd  = extract_rd(addi4);

I don't think so many local variables are a good idea, at least it doesn't do much to improve readability, except to make the code verbose.


PR: https://git.openjdk.java.net/riscv-port/pull/57

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