February 2022 Archives by author

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Starting: Mon Feb 7 02:19:15 UTC 2022
Ending: Mon Feb 28 11:22:02 UTC 2022
Messages: 51

[riscv-port] RFR: 8281967: riscv: Intrinsify bigIntegerLeftShift Taiping Guo
[riscv-port] RFR: 8282331: riscv: vector register should be saved when RVV is enabled Feilong Jiang
[riscv-port] RFR: 8282331: is_wide_vector should not depend on specific vector size [v2] Feilong Jiang
[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v3] Feilong Jiang
[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v4] Feilong Jiang
[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v5] Feilong Jiang
[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v5] Feilong Jiang
[riscv-port] Integrated: 8282331: riscv: is_wide_vector should not depend on specific vector size Feilong Jiang
[riscv-port] RFR: 8282415: riscv: Rename StubRoutines::riscv64 to StubRoutines::riscv Feilong Jiang
[riscv-port] RFR: 8282415: riscv: Rename StubRoutines::riscv64 to StubRoutines::riscv [v2] Feilong Jiang
[riscv-port] RFR: 8282415: riscv: Rename StubRoutines::riscv64 to StubRoutines::riscv [v2] Feilong Jiang
[riscv-port] Integrated: 8282415: riscv: Rename StubRoutines::riscv64 to StubRoutines::riscv Feilong Jiang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging Aleksey Shipilev
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Yadong Wang
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Yadong Wang
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v3] Yadong Wang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging Yadong Wang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging Yadong Wang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging [v2] Yadong Wang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging [v3] Yadong Wang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging [v4] Yadong Wang
[riscv-port] RFR: 8281632: riscv: Improve interpreter stack banging [v4] Yadong Wang
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp Fei Yang
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v3] Fei Yang
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Fei Yang
[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v5] Fei Yang
[riscv-port] RFR: 8282415: riscv: Rename StubRoutines::riscv64 to StubRoutines::riscv [v2] Fei Yang
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp Xiaolin Zheng
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Xiaolin Zheng
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Xiaolin Zheng
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Xiaolin Zheng
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v3] Xiaolin Zheng
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v2] Xiaolin Zheng
[riscv-port] RFR: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp [v3] Xiaolin Zheng
[riscv-port] Integrated: 8281731: riscv: Refactor instruction extraction code in nativeInst_riscv.h/cpp Xiaolin Zheng
[riscv-port] RFR: 8282415: riscv: Rename StubRoutines::riscv64 to StubRoutines::riscv [v2] Yanhong Zhu
[riscv-port] RFR: 8281967: riscv: Intrinsify bigIntegerLeftShift Yanhong Zhu
git: openjdk/riscv-port: riscv-port: 80 new changesets duke
git: openjdk/riscv-port: riscv-port: 14 new changesets duke
git: openjdk/riscv-port: riscv-port: 13 new changesets duke
git: openjdk/riscv-port: riscv-port: 15 new changesets duke
git: openjdk/riscv-port: riscv-port: 34 new changesets duke
git: openjdk/riscv-port: riscv-port: 16 new changesets duke
git: openjdk/riscv-port: riscv-port: 18 new changesets duke
git: openjdk/riscv-port: riscv-port: 36 new changesets duke
git: openjdk/riscv-port: riscv-port: 16 new changesets duke
git: openjdk/riscv-port: riscv-port: 7 new changesets duke
git: openjdk/riscv-port: riscv-port: 21 new changesets duke
git: openjdk/riscv-port: riscv-port: 18 new changesets duke
git: openjdk/riscv-port: riscv-port: 14 new changesets duke
git: openjdk/riscv-port: riscv-port: 9 new changesets duke

Last message date: Mon Feb 28 11:22:02 UTC 2022
Archived on: Mon Feb 28 11:22:09 UTC 2022

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