[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v6]

[Feilong Jiang]

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests:
> - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java
> - test/jdk/java/lang 
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213
> 
> Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.

Feilong Jiang has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains three additional commits since the last revision:

 - remove unused imm definition
 - remove unused instruction in riscv_b.ad
 - 8279344: riscv: RVB: Add bitwise rotation instructions

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/428e2151..92e21821

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=05
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=04-05

  Stats: 41 lines in 4 files changed: 4 ins; 8 del; 29 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39